(1) Technical Field
This invention relates to the general field of testing semiconductor devices, and more particularly, to a method for packaging a semiconductor chip in preparation for device testing during failure analysis.
(2) Description of the Prior Art
The following four documents relate to methods dealing with testing of integrated circuit devices.
U.S. Pat. No. 5,731,709 issued Mar. 24, 1998 to J. R. Pastore et al., shows methods and structures for testing a Ball Grid Array.
U.S. Pat. No. 5,783,461 issued Jul. 21, 1998 to D. R. Hembree discloses a temporary package for testing a semiconductor chip.
U.S. Pat. No. 5,567,884 issued Oct. 22, 1996 to G. T. Dickinson, shows a circuit board assemble torsion tester.
U.S. Pat. No. 5,598,036 issued Jan. 28, 1997 to T. H. Ho. shows a Ball Grid Array package.
The conductors used for interconnection within a semiconductor chip are extremely fine, being of the order of a few microns, or less, in width. The ability to construct such tiny conductors has made possible chips containing four to five orders of magnitude, and more, of interconnected components. This high level of integration has presented an enormous challenge, that is, at some point contact must be made between the chip and the external world where working to these tiny dimensions is not practical or even possible. The most widely used medium for connecting chips to one another and/or to the external world is a printed circuit board (PCB). The term PCB is used here in a general sense encompassing all types of printed circuit wiring, including what are known in the industry as cards and boards. The wiring on a PCB is much coarser than on a chip being typically measured in millimeters. It is not practical to connect a chip wiring directly to PCB wiring. An intermediate structure, capable of handling both ends of this wiring spectrum, is needed.
There are several types of these packages that include such rigid substrates as ceramics with straight-through vias, flexible polymer tape in tape automated bonding (TAB) with bumps or balls on either end, also, wafer-level assembly such as redistribution of peripheral I/Os to area array I/Os on chip and lead-on-chip (LOC).
Interconnections at the chip level were and are being achieved by wire bonding to plastic or ceramic single chip packages which are then bonded to printed wiring boards using surface mount technology (SMT). The trend is toward Flip Chip and Ball Grid Array (BGA) in the short term, and to direct-chip attach to the board in the long run. The board will be fabricated using fine line photolith via as contrast to drilled via in laminates and to photolith wiring on greensheets in ceramic boards.
The packaging technologies that span the microelectronics industry from consumer electronics to low-end systems to high-performance systems are very diverse. The number of chips needed to form a system in the past increased from a few, in consumer electronics, to several thousands, in supercomputers. Given this, the packaging hierarchical technologies necessary to interconnect all these chips become complex;
Semiconductor devices are presently supplied by chip manufacturers in die form, without wiring or electrical connection. A bare device in this configuration must be tested to assure a quality and reliability level prior to interconnection to a single level package. To certify a device as a good device the bare die must be tested and burned in. This has led to the development of temporary test carriers for performing burn in and testing of bare die. The temporary test carrier holds a single device and provides the electrical interconnection between the device and the device tester.
An improvement in packaging efficiency beyond ball grid arrays (BGAs) is being achieved by by so-called chip-scale of chip-size packages (CSP) which are hardly bigger than the chip itself. Similar to quad flat pack and BGA, CSP offers burn-in and testability of ICs prior to joining to the printed-wiring board. There are a number of types of these packages that include such rigid substrates as ceramics with straight-through vias, flexible polymer tape in tape automated bonding (TAB) with bumps or balls on either end, also, wafer-level assembly such as redistribution of peripheral I/Os to area array I/Os on chip and lead-on-chip.
The important parameters for developing a first-level package are numerous. In addition to supplying the required number of contacts for power and signal transmission, is arranging the desired number of wiring layers. Providing for thermal expansion compatibility with the chip, a thermal path for heat removal from the chip and to keep signal transmission delay and electrical noise to a minimum. Package sealing must ensure protection for both the package metallurgy and chip metallurgy. Minimum electrical delay requires a low dielectric constant. Low electrical noise requires low self-inductance's and low interline capacitance's and inductance's. Maximum heat removal requires high thermal conductivity. Maximum power distribution requires high electrical conductivity of package metallization, and high reliability requires a close thermal-expansion match between the chip and substrate.
The development cycle for first level packaging is extremely time consuming and costly. When the technology itself is developing in parallel, but on different time scales, resolution of the problems does not become easier. All of these issues are exacerbated by the continuing advance of VLSI and ultra large-scale integration (VLSI) technology, where exponential increases in the number of conductors are matched by its interconnected components making front and back-side failure analysis of the chip extremely important. It would be worthwhile to chip manufacturers if a quick and cost effective method was made available for preparing a new prototype chip sample with front and back side accessibility to do failure analysis.